I. Field
The present disclosure relates generally to electronics, and more specifically to techniques for testing an integrated circuit.
II. Background
Continual improvement in integrated circuit (IC) fabrication technology has enabled more and more complicated integrated circuits to be fabricated for a variety of applications. For example, an application specific integrated circuit (ASIC) may include one or more processors, memories, and other processing units. The integration of all of these circuit blocks on a single integrated circuit reduces cost and improves reliability.
Integrated circuits are typically manufactured via a complicated fabrication and testing process. After fabrication, the integrated circuit devices (or IC dies) are typically tested at the wafer level. Devices that pass wafer test are then packaged and tested at the final or package level. Devices that fail either wafer or final test are rejected.
Manufacturing resources are expended to package and final test each device that passes wafer test. Hence, it is desirable to identify as many defective devices as possible during the wafer test so that these devices are not unnecessarily packaged and final tested. To achieve this, a series of tests is typically performed at the wafer level. These tests often include a direct current (DC) leakage test that checks the pads on each device to make sure that these pads are not shorted or opened.
Wafer testing adds cost to the manufacturing process. Hence, a low-cost wafer probe scheme may be utilized, and this scheme may perform only a limited number of tests at the wafer level. The remaining tests (e.g., the pad DC leakage test) may be skipped at the wafer level and deferred until the package level. Each wafer level test that is deferred potentially results in defective devices (or test escapes) passing the wafer level testing. These defective devices would then be packaged and final tested, and unnecessary costs would be incurred to package and final test these defective devices.
There is therefore a need in the art for techniques to test an integrated circuit in a cost effective manner.